07.07.2010: Integrated Design, Verification and Reuse for FPGA design flows
1 month ago
WEDASoft Software and Technology Park Ljubljana are inviting you to attend an international seminar on Mentor Graphics' design flow for FPGA (and ASIC) designers, which will take place on 7 July at Technology Park Ljubljana.
Aim of the seminar is to present the enabling technologies that Mentor provides to enable companies and research establishments to more rapidly and effectively create and verify designs which incorporate a mix of new and existing RTL. MORE ...